1. Field of the Invention
The present invention relates to a semiconductor device to which high driving capability is required, and more particularly, to an improvement of driving capability of a transistor formed in a semiconductor device.
2. Description of the Related Art
A semiconductor device is manufactured by forming a large number of semiconductor chips on a semiconductor substrate and separating the semiconductor chips from one another to be settled in a package or the like for use. Along with development in manufacturing technology for a semiconductor device, the performance of transistors formed on a surface of the semiconductor chip has been improved in various aspects. With regard to a transistor with high driving capability, which can supply power to a load that requires large electric power, various technologies have been developed to decrease ON resistance (internal resistance of the transistor when the transistor is turned on). Currently, vertical double diffused MOS transistors (VDMOS) and trench gated MOS (UMOS) transistors, each having a structure in which electric current flows perpendicularly to the surface of a semiconductor substrate, are predominantly used for decreasing the ON resistance.
FIG. 10A is a sectional view of a semiconductor chip 009 in which a conventional transistor having high driving capability is formed. FIG. 10B is a sectional view of a conventional semiconductor device where a rear surface of the semiconductor chip 009 having a rear face electrode 004 is adhered through conductive paste 006 to a lead frame 005 that is used for packing the semiconductor chip 009. FIG. 2 is an equivalent circuit diagram (not shown in FIG. 10) of a transistor formed on an upper surface of the semiconductor chip 009 of FIG. 10. A source 016 of a transistor 011 is electrically connected to the rear surface electrode 004 of the semiconductor chip 009 via a semiconductor substrate forming the semiconductor chip 009, and power is supplied to the source 016 from the rear surface electrode 004 of the semiconductor chip 009. According to a control signal applied to a gate 014 of the transistor 011, power is supplied to a load (not shown) connected to a drain 015. Power is supplied to the source 016 of the transistor 011 of FIG. 2 from a surface 017 of the lead frame via a paste resistance 013 due to the conductive paste and a substrate resistance 012 (hereinafter the paste resistance 013 and the substrate resistance 012 are collectively referred to simply as parasitic resistance). The paste resistance 013 is the resistance of the conductive paste for adhering the semiconductor chip 009 to the lead frame 005. The substrate resistance 012 is the resistance of the semiconductor substrate which forms the semiconductor chip disposed between the rear surface electrode 004 to the source 016 of the transistor 011 and having a thickness D.
Conventionally, it was sufficient to decrease only the ON resistance, which was high as compared to the parasitic resistance, to supply high electric power to the load. However, in the above-described vertical device, despite the reduction in the ON resistance due to a development in micro fabrication technology, the parasitic resistance remains unchanged, and thus, the parasitic resistance is no longer negligible as an error in the ON resistance. In order to solve the problem, there has been adopted a back grind method for decreasing the thickness of the semiconductor substrate to decrease the substrate resistance 012 (see JP 2004-022899 A) and another method for decreasing of the paste resistance 013 through development of low resistance paste or the like (see JP 2003-016838 A).
The back grind method is to decrease the thickness D of the semiconductor substrate, as shown in FIG. 2A, but an excessive thinning in the thickness D causes lowering in the physical strength, which leads to a breaking of the semiconductor chip 009. Even if the above-described low resistance paste is used, the paste resistance 013 is more or less added serially as illustrated in FIG. 2, and thus the paste resistance can be decreased only to a certain extent. Here a problem occurs that the parasitic resistance cannot be decreased so much as compared to the ON resistance which was decreased remarkably due to the conventional art.